The present invention relates to a method for fabricating integrated circuits, and in particular, to a method of manufacturing stacked capacitors for a dynamic random access memory (DRAM).
Dynamic random access memories (DRAMs) are a widely used form of semiconductor memory. DRAMs are composed of a memory cell array and peripheral circuitry. Each memory cell array is formed of a plurality of memory cells for storing information. Typical memory cells are formed with a transistor for accessing a capacitor that stores charge. Of primary concern is maximizing the storage capacitance of each memory cell capacitor. This need is particularly acute in light of the demand for high density DRAMs, without increasing the chip area required to form the cell and, preferably, allowing a decrease in the chip area per cell.
One way to achieve greater capacitance per cell is to increase the surface area of the capacitor electrodes without increasing the respective cell area. As can be seen from the following equation, capacitance, C, is roughly determined by the thickness of the capacitor insulator (tox), the surface area of the capacitor electrodes (A), and the dielectric constant of the capacitor insulator (∈).
C=(∈xc2x7A)/tox
Increasing the surface area of the capacitor electrodes by forming the storage capacitor in a container like shape is well known in the art. To further increase circuit density in DRAMs stacked capacitors are used. These capacitors are actually stacked on top of the substrate, which may or may not include access devices. Two or more layers of a conductive material called electrodes are formed of polysilicon or poly are deposited over the substrate with dielectric layers sandwiched between each electrode.
U.S. Pat. No. 5,340,765 to Dennison et al., herein incorporated by reference, describes a method for further increasing the capacitance of a bottom electrode of such capacitors by forming the electrode surfaces with hemispherical grained polysilicon (HSG) which increases the surface area of the electrodes. First, a portion of an oxide layer covering access circuitry on a semiconductor wafer is removed to form a container. A bottom electrode is then formed by growing a first amorphous silicon layer. A first insulating layer is then formed on the first amorphous silicon layer. Then, a doped silicon layer is formed on the first insulating layer. Subsequently a second insulating layer is formed on the doped silicon layer. Finally, a second amorphous silicon layer is formed on the second insulating layer.
The insulating layers may be formed of oxide or nitride, and freeze the grain boundaries during deposition of the layers. Both the first and second amorphous silicon layers, and the insulating layers are formed relatively thin in relation to the doped silicon layer.
After formation of the layers, the wafer is planarized and the oxide etched to form standing containers which are then annealed to form HSG on both sides of the doped silicon layer. The insulating layers keep the doped silicon layer intact such that the silicon atoms do not penetrate silicon interfacing layers. Formation of a dielectric layer and top capacitor plate complete the capacitor formation.
There is a need for an improved stacked capacitor which may be etched better. There is a further need for a stacked capacitor container with improved HSG formation and better migration of dopants during HSG formation. There is yet a further need to improve the formation of multiple layers of silicon in a stacked capacitor container. There is also a need to enhance the capacitance of stacked capacitors, and provide a capacitor with higher breakdown voltage which is less susceptible to charge depletion.
A capacitor for a dynamic random access memory (DRAM) is formed by depositing a first layer of undoped silicon supported by a substrate, followed by a heavily doped silicon layer and a second layer of undoped silicon. The depositions are performed to minimize or eliminate formation of oxide layers between the layers. Etch back of the oxide leaves a capacitor bottom electrode having a layer of doped silicon with a xe2x80x9cpaintedxe2x80x9d layer of undoped silicon. Hemispherical grained polysilicon (HSG) is then formed in the painted layers by seeding and annealing.
Enhanced capacitance per cell area is provided by this roughening of the surfaces of the bottom electrode of a capacitor. HSG formation is enhanced by forming it in initially undoped layers of silicon. By limiting the formation of oxide between the silicon layers, dopants from the middle, heavily doped layer freely migrate during the formation of the HSG in the painted layers without significantly adversely affecting the HSG formation.
Many different types of capacitors may be formed using the above method. If stacked capacitors are formed, a xe2x80x9cpillarxe2x80x9d of doped silicon with xe2x80x9cpaintedxe2x80x9d layers of undoped silicon on either side form side walls. Following a planarization and an etch step, HSG formation then occurs on all exposed sides of the pillar electrode. Formation of a trench capacitor is formed in much the same way, with layers of undoped silicon sandwiching a layer of doped silicon in a trench formed in the substrate. At least one of the layers of undoped silicon is then selectively converted to HSG after the layers have been subjected to lithography and etching.
When forming a stacked capacitor cell, a first layer of BSG, PSG or undoped oxide is formed to a desired depth with respect to the pillars of silicon. This layer provides support to the pillars, allowing taller, and hence larger capacitors structures to be built. The first layer may be followed by a nitride layer to provide an etch stop for a BPSG layer which if formed on top of the nitride layer.
In one embodiment, the formation of the bottom electrode of a capacitor cell is accomplished in a single wafer tool capable of the depositions and seeding and annealing steps. This provides a process that is more efficient and less costly then the prior art since wafers need not be moved between steps. The undoped silicon layers are formed in a low pressure hydrogen environment by flowing silane or disilane while maintain total pressure below 1 atmosphere so that the layers are relatively smooth and exhibit minimal trapping of oxides. Therefore, it is also an advantage of the present invention that the containers of the present invention can be more closely spaced than prior art methods since it is easier to remove such oxides from the undoped silicon layers.
During annealing, the dopants of the doped silicon layer freely migrate into the undoped layers to dope those layers. This provides a further benefit in that the fabricated capacitors are less susceptible to depletion than their prior art counterparts. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.